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Multi-match packet classification on memory-logic trade-off FPGA-based architecture

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2 Author(s)
Carlos Zerbini ; Universidad Tecnológica Nacional, Department of Electrical Engineering, Córdoba, Argentina ; Jorge M. Finochietto

Packet processing is becoming much more challenging as networks evolve towards a multi-service platform. In particular, packet classification demands smaller processing times as data rates increase. To successfully meet this requirement, hardware-based classification architectures have become an area of extensive research. Even if Field Programmable Logic Arrays (FPGAs) have emerged as an interesting technology for implementing these architectures, existing proposals either exploit maximal concurrency with unbounded resource consumption, or base the architecture on distributed RAM memory-based schemes which strongly undervalues FPGA capabilities. Moreover, most of these proposals target best-match classification and are not suited for high-speed updates of classification rulesets. In this paper, we propose a new approach which exploits rich logic resources available in modern FPGAs while reducing memory consumption. Our architecture is conceived for multi-match classification, and its mapping methodology is naturally suited for high-speed, simple updating of the classification ruleset. Analytical evaluation and implementation results of our architecture are promising, demonstrating that it is suitable for line speed processing whith balanced resource consumption. With additional optimizations, our proposal has the potential to be integrated into network procesing architectures demanding all aforementioned features.

Published in:

High Performance Switching and Routing (HPSR), 2013 IEEE 14th International Conference on

Date of Conference:

8-11 July 2013