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Logic testing of bridging faults in CMOS integrated circuits

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2 Author(s)
Chess, B. ; Hewlett-Packard Co., Palo Alto, CA, USA ; Larrabee, T.

We describe a system for simulating and generating accurate tests for bridging faults in CMOS ICs. After introducing the Primitive Bridge Function, a characteristic function describing the behavior of a bridging fault, we present the Test Guarantee Theorem, which allows for accurate test generation for feedback bridging faults via topological analysis of the feedback-influenced region of the faulty circuit. We present a bridging fault simulation strategy superior to previously published strategies, describe the new test pattern generation system in detail, and report on the system's performance, which is comparable to that of a single stuck-at ATPG system. The paper reports fault coverage as well as defect coverage for the MCNC layouts of the ISCBS-85 benchmark circuits

Published in:

Computers, IEEE Transactions on  (Volume:47 ,  Issue: 3 )

Date of Publication:

Mar 1998

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