By Topic

A simplified architecture for module (2n+1) multiplication

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Yutai Ma ; Inst. of Comput. Technol., Acad. Sinica, Beijing, China

The module (2n+1) multiplication is widely used in the computation of convolutions and in RNS arithmetic and, thus, it is important to reduce the calculation delay. This paper presents a concept of a module (2n+1) carry save adder (MCSA) and uses two MCSAs to perform the residue reduction. We also apply Booth's algorithm to the module (2n+1) multiplication scheme in order to reduce the number of partial products. With these techniques, the new architecture reduces the multiplier's calculation delay and is suitable for VLSI implementation for moderate and large n (n⩾16)

Published in:

Computers, IEEE Transactions on  (Volume:47 ,  Issue: 3 )