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Optimal self-testing embedded parity checkers

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1 Author(s)
Nikolos, D. ; Dept. of Comput. Eng. & Inf., Patras Univ., Greece

This paper presents a new simple and straightforward method for designing Self-Testing Embedded (STE) parity checkers. The building block is the two-input XOR gate. During normal, fault-free operation, each XOR gate receives all possible input vectors. The great advantage of the proposed method is that it is the only one that gives, in a simple and straightforward way, optimal STE realizations with respect to the cost (number of XOR gates) and the speed (number of XOR gate levels)

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Computers, IEEE Transactions on  (Volume:47 ,  Issue: 3 )