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Testing for small-delay defects (SDDs) has become necessary for high-quality products (e.g., automotive applications) as technology scales further and functional frequency increases. Traditional timing-unaware transition-delay fault (TDF) ATPG is not adequate for detecting SDDs. Commercial timing-aware ATPGs suffer from large CPU runtime and huge pattern count. However, a small pattern set with high SDD coverage is desired by industry. In this paper, a comprehensive procedure named parametric pattern generation (PPG) is proposed in order to meet these requirements. In the evaluation phase of PPG, a new metric is proposed to represent pattern characteristics when detecting SDDs and gross TDFs. In the selection phase of PPG, pattern quality is considered by excluding detection redundancy. PPG is mathematically modeled and solved using the gradient descent concept. By learning from the previous pattern selection efficiency, a new selection is performed in a more effective way until the pattern set is finally generated. While utilizing PPG, the final pattern set can be framed in 1-detect volume with high SDD detection efficiency while meeting the target TDF coverage. Experimental results on both IWLS and ISCAS'89 benchmarks demonstrate the efficiency of the proposed method.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:32 , Issue: 10 )
Date of Publication: Oct. 2013