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In nanometer technologies, local interconnects are believed to cause a major impact on timing and power in VLSI circuits. To assess the impact of the interconnects on timing and power in a real high performance microprocessor design in a quantitative manner, this article presents results from an extensive study carried out on RTL-to-layout synthesized blocks in a 45-nm technology core. The study shows that the interconnects in these blocks account for 30% of the cycle time, on an average, on the worst internal timing paths and contribute nearly one-third to the power dissipation. This points to severity of impact due to the interconnects in today's high performance designs.