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A programmable multistage half-band FIR decimator for input data rates up to 2.56 MSPS

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2 Author(s)
Yoshida, T. ; Yokogawa Electr. Corp., Tokyo, Japan ; Kobayashi, H.

A multistage half-band FIR (finite impulse response) decimator has been implemented on a 40000-gate, 1.5-μm CMOS gate array, which dissipates 1.5 W at a clock rate of 25.6 MHz (a sampling rate of 2.56 MHz). The filter handles 20-b, 2.56-M sample/s input data. It has been tested for frequency shifting and zooming in a prototype FFT (fast Fourier transform) spectrum analyzer and has increased the frequency resolution by up to 217 times without aliasing, resulting in frequency resolution on the order of 20 mHz; it has a 96-dB dynamic range

Published in:

Instrumentation and Measurement Technology Conference, 1990. IMTC-90. Conference Record., 7th IEEE

Date of Conference:

13-15 Feb 1990