A MEMS-first fabrication process for integrating CMOS circuits with polysilicon microstructures

A MEMS-first fabrication process for integrating CMOS circuits with polysilicon micromechanical structures is described in detail. The overall process uses 17 masks to integrate a 1-metal, 2-poly, p-well based LOGOS CMOS process with a 3-poly sequence for microstructures. The microstructures are formed within recesses on the surface of silicon wafers such that their uppermost surfaces are coplanar with the remainder of the substrate. No special planarization technique, such as chemical-mechanical polishing (GMP), is used in the effort described here. Special aspects of the process include provisions to improve lithography within the recesses, to protect the microstructures during the circuit fabrication, and implement an effective lead transfer between the microstructures and the on-chip circuitry. The process is validated using a test vehicle that includes accelerometers and gyroscopes interfaced with voltage followers and switched-capacitor charge amplifiers. Measured transistor parameters match those obtained in standard CMOS.