Referenced Items are not available for this document.
With standard inverted-staggered amorphous silicon based TFT's, the size of active matrix liquid crystal displays is restricted by the RC time constant of the gate conductor. This RC delay can be reduced considerably by connecting the gate line through via holes to a bus run on the back side of the substrate. We use the SPICE model to examine the relationship between the RC delay and all important circuit parameters. The results show that with a low-resistance back line and only a few via holes per line, the delay can be reduced by nearly a factor of ten
Published in:
Electron Devices, IEEE Transactions on
(Volume:45
,
Issue:
1
)
Date of Publication: Jan 1998
- Page(s):
- 343 - 345
- ISSN :
- 0018-9383
- INSPEC Accession Number:
- 5812000
- Digital Object Identifier :
- 10.1109/16.658856
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Jan 1998
- Sponsored by :
- IEEE Electron Devices Society
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