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Scaling trends for device performance and reliability in channel-engineered n-MOSFETs

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5 Author(s)
Williams, S.C. ; Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA ; Hulfachor, R.B. ; Kim, K.W. ; Littlejohn, M.A.
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Channel-engineered MOSFETs with retrograde doping profiles are expected to provide increased carrier mobility and immunity to short channel effects. However, the physical mechanisms responsible for device performance of retrograde designs in the deep-submicron regime are not fully understood, and general device scaling trends are not well documented. Also, little effort has been devoted to the study of hot-electron-induced device degradation. In this paper, we employ a comprehensive simulation methodology to investigate scaling and device performance trends in channel-engineered n-MOSFETs. The method features an advanced ensemble Monte Carlo device simulator to extract hot-carrier reliability for super-steep-retrograde and more conventional silicon n-MOS designs with effective channel lengths scaled from 800 to 100 nm. With decreasing channel length, our simulations indicate that the retrograde design shows increasingly less total hot-electron injection into the oxide than the conventional design. However, near the 100-nm regime, the retrograde design provides less current drive, loses its advantage of higher carrier mobility, and exhibits much greater sensitivity to hot-electron-induced interface states when compared to the conventional device

Published in:

Electron Devices, IEEE Transactions on  (Volume:45 ,  Issue: 1 )

Date of Publication:

Jan 1998

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