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A new simulation model for plasma ashing process-induced oxide degradation in MOSFET

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3 Author(s)
Kuo-Feng You ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Ming-Chien Chang ; Ching-Yuan Wu, Ph.D.

Plasma ashing process-induced oxide damage is studied quantitatively in this paper. To simulate thin gate-oxide damage due to the plasma ashing process, a new equivalent circuit model is proposed by including a differential capacitance, a parasitic resistance, an offset flatband voltage, and the effects of feedback on the interface-state and trapped oxide charge densities generated during the plasma ashing process. According to this new model, computation of gate oxide charging current is performed by correlating to the latent interface-state density. The test n-MOSFET devices, including different antenna-ratios are measured, and excellent agreement is obtained as compared with measured results. Moreover, the deficiency of the previous model is stated and compared. In addition, the effects of substrate doping concentration on plasma-induced oxide damage are also investigated as well as those of plasma ion density, plasma uniformity, thin gate-oxide thickness. Therefore, the relationships between interface states/oxide traps and antenna ratio are linked to provide a guideline for circuit designers and the plasma ashing process-induced damage can be predicted

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Electron Devices, IEEE Transactions on  (Volume:45 ,  Issue: 1 )