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Effect of floating-body charge on SOI MOSFET design

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3 Author(s)
Wei, A. ; Microsystems Technol. Lab., MIT, Cambridge, MA, USA ; Sherony, M.J. ; Antoniadis, D.A.

This work presents a new method for assessing the effect of floating-body charge on a fully- and partially-depleted Silicon-on-Insulator (SOI) MOSFET device design space. Floating-body effects under transient conditions are incorporated into the device design parameters threshold voltage VT and off-current I0FF using calibrated two-dimensional (2-D) device simulation. Simulation methodology which reveals the worst-case bounds of the device design parameters, from idle to switching-steady-state, is presented and applied to a CMOS inverter example. Using this methodology, the worst-case shifts in VT and I0FF due to hysteretic floating-body charge are quantified for devices in L eff=0.2- and 0.1-μm design spaces. Methods to reduce floating-body effects are discussed including a demonstration of how reducing the effective bulk carrier lifetime widens the 0.1-μm design space

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Electron Devices, IEEE Transactions on  (Volume:45 ,  Issue: 2 )