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Matrix unit cell scheduler (MUCS) for input-buffered ATM switches

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3 Author(s)
Haoran Duan ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; J. W. Lockwood ; Sung Mo Kang

This paper presents a novel matrix unit cell scheduler (MUCS) for input-buffered asynchronous transfer mode (ATM) switches. The MUCS concept originates from a heuristic strategy that leads to an optimal solution for cell scheduling. Numerical analysis indicates that input-buffered ATM switches scheduled by MUCS can utilize nearly 100% of the available link bandwidth. A transistor-level MUCS circuit has been designed and verified using HSPICE. The circuit features a regular structure, minimal interconnects, and a low transistor count. HSPICE simulation indicates that using 2-μm CMOS technology, the MUCS circuit can operate at clock frequency of 100 MHz.

Published in:

IEEE Communications Letters  (Volume:2 ,  Issue: 1 )