Cart (Loading....) | Create Account
Close category search window
 

Matrix unit cell scheduler (MUCS) for input-buffered ATM switches

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Haoran Duan ; Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA ; Lockwood, J.W. ; Kang, S.M.

This paper presents a novel matrix unit cell scheduler (MUCS) for input-buffered asynchronous transfer mode (ATM) switches. The MUCS concept originates from a heuristic strategy that leads to an optimal solution for cell scheduling. Numerical analysis indicates that input-buffered ATM switches scheduled by MUCS can utilize nearly 100% of the available link bandwidth. A transistor-level MUCS circuit has been designed and verified using HSPICE. The circuit features a regular structure, minimal interconnects, and a low transistor count. HSPICE simulation indicates that using 2-/spl mu/m CMOS technology, the MUCS circuit can operate at clock frequency of 100 MHz.

Published in:

Communications Letters, IEEE  (Volume:2 ,  Issue: 1 )

Date of Publication:

Jan. 1998

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.