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Low-power buffered clock tree design

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2 Author(s)
Vittal, A. ; Silicon Graphics Inc., Mountain View, CA, USA ; Marek-Sadowska, M.

We address the problem of low-power reliable clock tree design in this paper. We study the scaling of clock power dissipation with increasing die sizes, number of receivers, and operating frequencies. The analysis shows that buffering only at the root of the tree is not scalable. However, when buffered clock trees are allowed, the classical H tree is suboptimal in terms of both area and power dissipation. We show that the new power minimization problem is NP hard, and we propose a novel algorithm for low-power clock network design. Our algorithm designs the tree topology and inserts buffers simultaneously. The clock skew is guaranteed to be small in the presence of correlated process variations. Wire sizing is used when necessary, and clock skew can be inserted intentionally if required. The results obtained by our algorithm on benchmark problem instances are significantly better than previous approaches in terms of power dissipation, wire length, rise times, and buffer area. We report HSPICE simulation results for the clock trees designed by the new algorithm.

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Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:16 ,  Issue: 9 )