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Face detection is an important aspect for biometrics, video surveillance and human computer interaction. Owing to the complexity of the detection algorithms any biometric system requires a huge amount of computational and memory resources. A direct software-like implementation of any detection algorithm on a low speed, low resource, low power system on chip (SoC) is not feasible. Instead, a software-hardware codesign approach can be used to build hardware accelerators for the most computational consuming parts of the detection algorithms. Therefore the authors propose a compliant advanced microcontroller bus architecture (AMBA) bus hardware IP, a modularised, highly configurable, low power and technology independent core written in an hardware description language (HDL) language. The IP core accelerates Viola-Jones algorithm considered to be one of the most used algorithms for face detection. The hardware accelerator IP is used in an embedded face detection system built around the LEON3 Sparc V8 processor. The authors present the methodology, challenges and performance results for software, hardware and system level design. For the mentioned system the authors have obtained an acceleration factor of 10-12 when using the hardware accelerator in comparison with the software only traditional approach.