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A low-power, high-speed full adder (FA), abbreviated as LPHS-FA, is presented as an elegant way to reduce circuit complexity and improve the performance thereof. Employing as few as 15 MOSFETs in total, an LPHS-FA requires 60-73% fewer transistors than other existing FAs with drivability. For validation purpose, HSPICE simulations are conducted on all the proposed and referenced FAs based on the TSMC 0.18-μm CMOS process technology. The LPHS-FA is found to provide a 20.4-21.2% power saving, a 12.3-67.0% delay time reduction and a 35-102% reduction in power delay product compared with the referenced FAs. In short, an LPHS-FA is presented in a concise form as a high-performance FA in practical applications.