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Clock-domain crossing (CDC) faults require careful post-silicon testing for multiclock circuits. Even when robust design methods based on synchronizers and design verification techniques are used, process variations can introduce subtle timing problems that affect data transfer across clock-domain boundaries for fabricated chips. We integrate solutions for detecting and locating CDC faults, and ensuring post-silicon recovery from CDC failures. In the proposed method, CDC faults are located using a CDC-fault dictionary, and their impact is masked using post-silicon clock-path tuning. To quantify the impact of process variations in the transfer of data at clock domain boundaries of multiclock circuits and to validate the proposed error-recovery method, we conducted a series of HSpice simulations using a 45-nm technology. The results demonstrate high incidence of process variation-induced violation of setup and hold time at the boundary flip-flops, even when synchronizer flip-flops are employed. The results also confirm the effectiveness of the proposed error-recovery scheme in recovering from CDC failures.