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Chip surface topography after chemical mechanical polishing (CMP) process is determined by both process conditions and layout geometric characteristics. In Cu interconnect CMP, slurry used in P3 stage may have a higher copper remove rate or a higher dielectric remove rate, and this difference in slurry selectivity will result in different surface topography. In order to study the influence of slurry selectivity on CMP pattern effects, test chips containing different line width/space arrays are designed and they are fabricated in two typical process conditions. Surface topography of the arrays is measured by an atomic force profiler (AFP) and cross-sectional images are acquired using a scanning electron microscope (SEM) after CMP. Measurement results in two process conditions are compared, and the effects of layout geometric parameters on metal dishing are also analyzed. For large features, dishing changes obviously with density; while for small features, dishing is less affected by density. Also, a new phenomenon is observed: morphology of the copper line after P3 changes with width/space parameters. Line edges are protruding in some arrays, and this protrusion disappears in others. This phenomenon is believed to be due to different selectivity of the slurries used in P2 and P3 stages.