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90nm WAl2O3TiWCu 1T1R CBRAM cell showing low-power, fast and disturb-free operation

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8 Author(s)

In this paper we demonstrate excellent memory performances of a 90nm CMOS-friendly WAl2O3TiWCu CBRAM cell integrated in a 1T1R configuration and withstanding the back-end of line thermal budget of 400°C. The cell exhibits low-power and highly controlled set and reset operations, allowing reversible multilevel programming controlled by both the set current and the reset voltage. Low-voltage (<;3V) operation is obtained down to 10ns-long write pulse both for set and reset, and allowing >106 write endurance with a 2-decade memory window. State stability is assessed up to 125°C. Moreover, due to low slope of the voltage-log(time) relationship the cell also shows excellent voltage-disturb immunity assessed up to +/-0.5V and extrapolated to 10 years.

Published in:

Memory Workshop (IMW), 2013 5th IEEE International

Date of Conference:

26-29 May 2013