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Supply-Noise-Resilient Design of a BBPLL-Based Force-Balanced Wheatstone Bridge Interface in 130-nm CMOS

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5 Author(s)
Van Rethy, J. ; Dept. of Electr. Eng. (ESAT), KU Leuven, Leuven, Belgium ; Danneels, H. ; De Smedt, V. ; Dehaene, W.
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An energy-efficient and supply- and temperature-resilient resistive sensor interface in 130-nm CMOS technology is presented. Traditionally resistive sensors are interfaced with a Wheatstone bridge and an amplitude-based analog-to-digital converter (ADC). However, both the unbalanced Wheatstone bridge and the ADC are highly affected by supply voltage variations, especially in smaller CMOS technologies with low supply voltages. As alternative to ratiometric measuring, this paper presents a force-balanced Wheatstone bridge interface circuit with a highly digital architecture that combines the advantage of energy-efficient sensing with highly improved overall PSRR and temperature resilience in one circuit. The prototyped circuit has a noise-frequency-independent PSRR of 52 dB, even for supply-noise amplitudes up to +10 dB FS. The maximum absolute output error in a supply voltage range of 0.85-1.15 V is only 0.7%, while the maximum absolute output error in a temperature range of 100°C is only 0.56% or 56 ppm/°C. The complete interface is prototyped in 130-nm CMOS and consumes 124.5 μW from a 1-V supply with a 10-kHz input bandwidth and 10.4-b resolution and 8.9-b linearity, resulting in a state-of-the-art sensor figure of merit of 13.03 pJ/bit-conversion.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 11 )