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Energy limits in A/D converters

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1 Author(s)
Murmann, B. ; Dept. of Electr. Eng., Stanford Univ., Stanford, CA, USA

Driven by ever-increasing application demands, the energy expended per A/D conversion has improved substantially over the last decade. This paper surveys the most recent trends and investigates practical energy limits of A/D converter architectures that are commonly employed in fine-line CMOS technology. We observe that today's most efficient converters operate at about two orders of magnitude above the classical 8kT·SNR thermal limit. Furthermore, it is shown that a large fraction of today's designs have approached ideal thermal limit lines, corresponding to a four-fold increase in energy per bit of resolution.

Published in:

Faible Tension Faible Consommation (FTFC), 2013 IEEE

Date of Conference:

20-21 June 2013

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