By Topic

Process integration of 3D Si interposer with double-sided active chip attachments

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

19 Author(s)
Pei-Jer Tzeng ; Electron. & Optoelectron. Res. Labs. (EOL), Ind. Technol. Res. Inst. (ITRI), Hsinchu, Taiwan ; Lau, J.H. ; Chau-Jie Zhan ; Yu-Chen Hsin
more authors

A double-sided Si passive interposer connecting active dies on both sides for a 3D IC integration is investigated. This interposer is 100μm-thick with 10μm-diameter TSVs (through silicon vias), 3 RDLs (redistribution layer) on its front-side, 2 RDLs on its backside. It supports 2 active dies on its frontside and 1 active die at its backside. The present study focuses on the process integration of the passive interposer, double-sided chip assembly process, and passive electrical characterization.

Published in:

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Date of Conference:

28-31 May 2013