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Development of 3D through silicon stack (TSS) assembly for wide IO memory to logic devices integration

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8 Author(s)

Memory to logic system architecture using through silicon stacking (TSS) becomes one of the most promising candidates for the first commercial 3D device due to the continuous demands for small form factor, lower power consumption and higher data bandwidth of mobile devices. Main challenges to bring 3D TSS technology to the volume production level are establishing a cost effective supply chain and building a reliable manufacturing processes. This paper will report recent progress of wide IO memory to high count TSV logic device assembly development work. 28nm node TSV test vehicles were fabricated by the foundry and assembled at Amkor. Successful integration of functional memory wide IO chip with less than a millimeter package thickness form factor was achieved. We believe that this is the industry first demonstration of functional wide IO memory to 28nm logic device assembly using 3D package architecture with such a thin form factor. For assembly process enabling work, we will present high quality microbump joint with minimum 40μm pitch, key challenges with their mitigations and environmental reliability test results which exceeded reliability spec for the mobile applications.

Published in:

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Date of Conference:

28-31 May 2013