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Thermo mechanical challenges for processing and packaging stacked ultrathin wafers

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5 Author(s)

During the manufacturing of 3D stacked-die packaging structures, different operations such as micro bumps formation, underfilling, flip chip and overmold curing will introduce residual stresses, which will interact with subsequent service loads applied to the package and may also influence the growth of cracks in critical locations. In this work, the packaging of a 3D-RAM mounted on a logic die is simulated taking the thermal history into account by simulating the main process steps and by adapting the mechanical stiffness of the materials. The resulting stress/strain tensors are taken as initial condition of the following step and the mechanical properties of the new materials added to the process are adapted. The resulting stresses and strains at every step are extracted from the model to identify the most critical processing steps. A die to wafer approach is used for the stacking process as it allows the integration of heterogeneous and different die size. In this work we show the simulation results after each processing step for two die stacking approaches: (a) mold wafer reconstruction, (b) window wafer reconstruction. In the first case, high warpage is observed. In the second case, warpage is reduced but high stress concentration is observed in the logic die.

Published in:

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Date of Conference:

28-31 May 2013