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Single-Event Performance and Layout Optimization of Flip-Flops in a 28-nm Bulk Technology

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9 Author(s)
Lilja, K. ; Robust Chip Inc., Pleasanton, CA, USA ; Bounasser, M. ; Wen, S.-J. ; Wong, R.
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Alpha, neutron, and heavy-ion single-event measurements were performed on both high-performance and hardened flip-flop designs in a 28-nm bulk CMOS technology. The experimental results agree very well with simulation predictions and confirm that event error rates can be reduced dramatically using effective layout design.

Published in:

Nuclear Science, IEEE Transactions on  (Volume:60 ,  Issue: 4 )

Date of Publication:

Aug. 2013

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