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Thin-film SOI CMOS transistors with p+-polysilicon gates

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4 Author(s)
Davis, J.R. ; British Telecom Res. Lab., Ipswich, UK ; Armstrong, G.A. ; Thomas, N.J. ; Doyle, A.

A comparison is given of the use of p+-polysilicon and n+-polysilicon as the gate material for high-performance CMOS processes in fully depleted, thin SOI (silicon on insulator) films. Experimental devices on Simox substrates are compared with numerical simulations. It is found that n-channel transistors with p-poly gates require lower channel doping levels than their n-poly counterparts, leading to higher gains and easier control of the threshold voltage. The lower electric fields in the p-poly transistor also result in improved drain breakdown characteristics. Control of the subthreshold and punch-through characteristics of the p-poly device requires the use of very thin films when there is significant fixed positive charge at the interface with the buried oxide

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Electron Devices, IEEE Transactions on  (Volume:38 ,  Issue: 1 )