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Design of fault-diagnosable and repairable folded PLAs for yield enhancement

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3 Author(s)
Chin-Long Wey ; Dept. of Electr. Eng., Michigan State Univ., East Lansing, MI, USA ; Tsin-Yuan Chang ; Ding, J.

A defect-tolerant PLA (programmable logic array) design with a simple column folding technique to enhance the probe yield is presented. The results show that the design requires less die size than a previous design, while still achieving full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults. The design concept is readily extended to other folding techniques. Among the various folding techniques, the trade-offs are the density improvement and regularity, i.e. the density improvement is often paid for as higher irregularity. In fact, the irregularity often results in a higher defect density. It is concluded that a density improvement does not guarantee a higher overall yield

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Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 1 )