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Advances in 3-D integrated circuit (3-DIC) technology have allowed for advantages in integration, system speed, and power consumption for digital systems. In systems operating at very high data rates with large data width, the effect of simultaneous switching noise (SSN) can, however, drastically affect system performance. Therefore, the effect of SSN in the power delivery network (PDN) design of a through silicon via (TSV)-based 3-D stack has been investigated in this paper, and eye diagrams have been simulated in each level of the stack to analyze power supply noise and transition jitter. Using a novel PDN design concept based on constant voltage power transmission lines, it is shown that this new PDN design can significantly improve signal quality in a 3-DIC application. The 3-D system considered here consists of a PCB, an interposer, and three IC dies. Each IC contains a TSV layer, PDN, and digital logic.