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Low-energy asynchronous memory design

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2 Author(s)
J. A. Tierno ; California Inst. of Technol., Pasadena, CA, USA ; A. J. Martin

We introduce the concept of energy per operation as a measure of performance of an asynchronous circuit. We show how to model energy consumption based on the high-level language specification. This model is independent of voltage and timing considerations. We apply this model to memory design. We show first how to dimension a memory array, and how to break up this memory array into smaller arrays to minimize the energy per access. We then show how to use cache memory and pre-fetch mechanisms to further reduce energy per access

Published in:

Advanced Research in Asynchronous Circuits and Systems, 1994., Proceedings of the International Symposium on

Date of Conference:

3-5 Nov 1994