Sub-50-nm InGaAs MOSFET with n-InP source on Si substrate

We demonstrated a sub-50-nm InGaAs 5-nm/InP 5-nm MOSFET with an n-InP source on a Si substrate using a 5-nm Al
2
O
3
dielectric. In the measurement of the fabricated device, the maximum drain current and the peak transconductance at V
D
= 0.5 V were 0.9 mA/µm and 0.8 mS/m, respectively. The threshold voltage was 0.09 V, and the drain-induced barrier lowering was 378 mV/V. From the channel length dependence, clear suppression of the short channel effect by the 5-nm-thick Al
2
O
3
gate dielectric and the extremely thin body III-V-OI structure was confirmed.