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Instruction scheduling for power reduction in processor-based system design

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4 Author(s)
H. Tomiyama ; Dept. of Comput. Sci. & Commun. Eng., Kyushu Univ., Fukuoka, Japan ; T. Ishihara ; A. Inoue ; H. Yasuura

This paper proposes an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm

Published in:

Design, Automation and Test in Europe, 1998., Proceedings

Date of Conference:

23-26 Feb 1998