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Leakage tests have been a challenge for through-silicon vias (TSVs) in a 3-D IC. Most existing methods are still inadequate in terms of the range of testable leakage currents. In this paper, we borrow the wisdom of the IO-pin leakage test while enhancing it with two features. First, we make it more suitable for a TSV, which has a much smaller capacitance than an IO pin. Second, we support a wide range of leakage test (e.g., from 0.125 μA to 16 μA), and thereby allowing for flexible test threshold setting and leakage characterization. To achieve this goal, we present two sets of techniques-1) wait-time generation by programmable delay line, and 2) wait-time propagation with a self-timed timing control scheme to overcome the timing skew problem due to signal routing. We demonstrate that the entire scheme can be done in only logic gates, making it easy to integrate into the common design flow.