By Topic

Verification by simulation comparison using interface synthesis

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
C. Hansen ; FZI, Karlsruhe, Germany ; A. Kunzmann ; W. Rosenstiel

One of the main tasks within the high-level synthesis (HLS) process is the verification problem to prove automatically the correctness of the synthesis results. Currently, the results are usually checked by simulation. In consequence, both the behavioral specification and the HLS results have to be simulated by the same set of test vectors. Due to the HLS and the inherent changes in the cycle-by-cycle behaviour, the synthesis results require an adaption of the initial test vector set. This reduces the advantage gained by using the automated HLS process. In order to decrease these simulation efforts, in this paper a new method is presented that enables the usage of the same simulation vectors at both abstraction levels and the execution of an automated simulation comparison

Published in:

Design, Automation and Test in Europe, 1998., Proceedings

Date of Conference:

23-26 Feb 1998