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The increasing demand for more secure operation of space missions has led to emergence of cryptographic mechanisms aboard spacecrafts. However, cryptographic applications are extremely sensitive to bit-flips caused by radiation-induced single event upsets (SEUs). A traditional approach to mitigate SEUs in space applications has been the triple modular redundancy (TMR). However, such technique incurs large overheads in implementation area and power. An efficient approach to achieve fault tolerance in the secure hash standard (SHS) and in the keyed-hash message authentication code (HMAC) is introduced. When compared with TMR the proposed scheme not only achieves higher resistance against SEUs, but it also reduces implementation area requirements and power consumption. Results obtained through field-programmable gate array (FPGA) implementation show that HMAC/SHA-512 (secure hash algorithm) utilizes, on average, 53% less area and less power compared with the traditional TMR technique. Furthermore, the memory and registers of the HMAC/SHA-512 module are approximately 171 and 491 times more resistant against SEUs than TMR. This research is crucial for enabling the efficient employment of security mechanisms onboard space systems.