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A 4.8-GHz Dividerless Subharmonically Injection-Locked All-Digital PLL With a FOM of - 252.5 dB

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3 Author(s)
I-Ting Lee ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Kai-Hui Zeng ; Shen-Iuan Liu

A subharmonically injection-locked all-digital phase-locked loop (ADPLL) is presented to achieve both low power and low phase noise simultaneously. This ADPLL uses a bang-bang phase detector to maintain the phase locking without a time-to-digital converter, and the dividers can be disabled to reduce the power. In addition, a subharmonically injection-locked technique is used to achieve a low phase noise. This ADPLL is fabricated in a 40-nm complementary metal-oxide-semiconductor technology. Its power consumption is 3.661 mW for a supply voltage of 1.1 V. The measured phase noise is equal to -122.33 dBc/Hz at an offset frequency of 1 MHz. The integrated root-mean-square jitter is 123.4 fs for the offset frequency from 1 kHz to 100 MHz. The calculated figure of merit is equal to -252.5 dB.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:60 ,  Issue: 9 )