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Dummy Gate-Assisted n-MOSFET Layout for a Radiation-Tolerant Integrated Circuit

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2 Author(s)
Min Su Lee ; Division of Electrical Engineering, School of Electrical Engineering & Computer Science, Korea Advanced Institute of Science and Technology, Daejeon, Republic of Korea ; Hee Chul Lee

A dummy gate-assisted n-type metal oxide semiconductor field effect transistor (DGA n-MOSFET) layout was evaluated to demonstrate its effectiveness at mitigating radiation-induced leakage currents in a conventional n-MOSFET. In the proposed DGA n-MOSFET layout, radiation-induced leakage currents are settled by isolating both the source and drain from the sidewall oxides using a p+ layer and dummy gates. Moreover, the dummy gates and dummy Metal-1 layers are expected to suppress the charge trapping in the sidewall oxides. The inherent structure of the DGA n-MOSFET supplements the drawbacks of the enclosed layout transistor, which is also proposed in order to improve radiation tolerance characteristics. The Vg-Id simulation results of the DGA n-MOSFET layout demonstrated the effectiveness of eliminating such radiation-induced leakage current paths. Furthermore, the radiation exposure experimental results obtained with the fabricated DGA n-MOSFET layout also exhibited good performance with regard to the total ionizing dose tolerance.

Published in:

IEEE Transactions on Nuclear Science  (Volume:60 ,  Issue: 4 )