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Superior Improvements in GIDL and Retention by Fluorine Implantation in Saddle-Fin Array Devices for Sub-40-nm DRAM Technology

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11 Author(s)
Chia-Ming Yang ; Dept. of Electron. Eng., Chang Gung Univ., Taoyuan, Taiwan ; Jer-Chyi Wang ; Wei-Ping Lee ; Chien-Chi Lee
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A highly improved method to reduce gate-induced drain leakage and retention fail bit counts is proposed for use in the sub-40-nm dynamic random access memory technologies. Fluorine (F) implantation with different dose post-gate oxidation is used for investigating the performance of saddle-fin (S-Fin) array devices. Significantly lower retention fail counts of 35% are achieved in the S-Fin device using a medium dosage of F implantation. Random telegraph signal-like fluctuation can also be improved using the proposed F implantation method. Trap passivation by F atoms in the source and the drain areas could have led to the improvements seen in the experiments.

Published in:

Electron Device Letters, IEEE  (Volume:34 ,  Issue: 9 )