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FPGA adders: performance evaluation and optimal design

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2 Author(s)
Shanzhen Xing ; Hong Kong Univ., Hong Kong ; W. W. H. Yu

Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders

Published in:

IEEE Design & Test of Computers  (Volume:15 ,  Issue: 1 )