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A CMOS binary pattern classifier based on Parzen's method

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1 Author(s)
Coultrip, R. ; Interplay Productions, Anaheim, CA, USA

Biological circuitry in the brain that has been associated with the Parzen method of classification inspired an analog CMOS binary pattern classifier. The circuitry resides on three separate chips. The first chip computes the closeness of a test vector to each training vector stored on the chip where “vector closeness” is defined as the number of bits two vectors have in common above some thresholds. The second chip computes the closeness of the test vector to each possible category where “category closeness” is defined as the sum of the closenesses of the test vector to each training vector in a particular category. Category closenesses are coded by currents which feed into an “early bird” winner-take-all circuit on the third chip that selects the category closest to the test vector. Parzen classifiers offer superior classification accuracy than the common nearest neighbor Hamming networks. A high degree of parallelism allows for O(1) time complexity and the chips are tillable for increased training vector storage capacity. Proof-of-concept chips were fabricated through the MOSIS chip prototyping service and successfully tested

Published in:

Neural Networks, IEEE Transactions on  (Volume:9 ,  Issue: 1 )

Date of Publication:

Jan 1998

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