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A BiCMOS front-end system with binary delay line for capacitive detector read-out

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1 Author(s)
Wulleman, J. ; Dept. of Electron. Eng., Tokyo Univ., Japan

As part of the entire readout chip, a low-power high-gain transresistance amplifier has been developed, followed by a high-speed, low-power small offset comparator and a binary delay line. The amplifier is balanced, fully differential in circuit topology, and symmetrical in layout, making it radiation tolerant and relatively insensitive to varying magnetic fields. Also, the comparator is fully symmetrical with a balanced input stage. Before irradiation (pre-rad) the transresistance amplifier has a measured differential gain of 110 mV/4 fC, an average 10/90% rise time (t10/90%) of 20 to 50 ns depending on the bias conditions, a noise figure of 433⊕93.(Ct)1.08 (where the symbol ⊕ stands for √(()2+() 2)) electrons (e-), and a power consumption of 750 μW. The comparator uses bipolar transistors in the regenerative stage resulting in a small offset, a sensitivity <1.5 mV, and a power consumption of ≈350 μW at 40 MHz. The maximum pre-rad frequency at which the comparator is still functioning correctly is ≈100 MHz. Pre-rad, the binary delay line has a delay of 2.1 μs at 40 MHz and a power consumption of ≈450 μW/channel for a four-channel design. The complete readout channel-amplifier, comparator, and binary delay line-consumes ≈1.5 mW. The entire readout system was implemented in the radiation-hard 0.8-μm SOI-SIMOX BiCMOS-PJFET technology of DMILL

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:33 ,  Issue: 1 )