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An integrated 200-MHz 3.3-V BiCMOS class-IV partial-response analog Viterbi decoder

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3 Author(s)
M. H. Shakiba ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; D. A. Johns ; K. W. Martin

Analog Viterbi decoders have recently been shown to be viable alternatives to their digital counterparts. In fact, a commercial analog class-IV partial-response sequence detector for magnetic read channels has already been reported. Analog decoders offer the advantages of reduced power and size primarily due to the elimination of the A/D. The analog Viterbi decoder described here is less complex and more robust compared to other reported realizations. The decoder is based on a new derivation of the difference-metric algorithm which is developed from an analog implementation perspective. This has resulted in a decrease in hardware complexity thereby making an analog approach more attractive for today's demanding high-speed, low-power, and small-size applications, such as magnetic disk-drive storage systems. The decoder was fabricated in a 0.8-μm BiCMOS process. It consists of two time-interleaved dicodes and the interleaving circuitry. The decoder was tested at up to 100 MS/s. However, since each dicode was also tested at this speed, the class-IV decoder should be capable of operating at 200 MS/s. Direct experiments at this speed were not possible due to the test equipment limitations. The chip consumes 30 mW from a 3.3-V power supply and occupies a core area of 0.5 mm2

Published in:

IEEE Journal of Solid-State Circuits  (Volume:33 ,  Issue: 1 )