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Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages

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3 Author(s)
Jian Liu ; Dept. of Electr. Eng., Columbia Univ., New York, NY, USA ; Nowick, S.M. ; Mingoo Seok

With the recent advancement of nanometer process technologies and the growing interest in scaled supply voltage operation, we are facing increasing challenges to robust design due to process, voltage, and temperature (PVT) variation. One promising direction is to consider asynchronous pipelines, which eliminate the need for fixed-rate clock distribution. However, while conventional single-rail bundled-data asynchronous pipeline styles can mitigate global and spatial variations by closely placing the delay elements to their corresponding pipeline stages, random variations are currently not effectively handled. In particular, timing margins must be added to the matched delay elements in each stage, resulting in reduced performance and increased leakage power consumption. Building upon a well-known asynchronous pipeline, MOUSETRAP, this paper proposes a scheme to mitigate the impact of random PVT variations over a range of supply voltages. We introduce the notion of soft latching for asynchronous pipelines: allowing data registers to latch their incoming data during a wider sampling window. As a result, the pipeline operates correctly even with random PVT variation-induced delay mismatch between a bundled delay and its corresponding pipeline stage. However, the inclusion of soft latching can exacerbate hold time violations, these are mitigated through a novel protocol modification. The new asynchronous soft-latching scheme shows significant energy-efficiency and performance improvement over the conventional margining approach, it also robustly operates down to 0.3V even in the presence of random process variations.

Published in:

Asynchronous Circuits and Systems (ASYNC), 2013 IEEE 19th International Symposium on

Date of Conference:

19-22 May 2013