Cart (Loading....) | Create Account
Close category search window

VLSI implementation of 350 MHz 0.35 μm 8 bit merged squarer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $31
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Kolagotla, R.K. ; Lucent Technol., Allentown, PA, USA ; Griesbach, W.R. ; Srinivas, H.R.

The partial-products of a squarer are symmetric about the diagonal, and are typically folded and shifted to reduce the depth of the array. The authors describe a technique that further reduces the critical path by merging the partial-products along the diagonal with the rest of the folded array. An 8 bit squarer operates at 350 MHz in the Lucent 0.35 μm CMOS process

Published in:

Electronics Letters  (Volume:34 ,  Issue: 1 )

Date of Publication:

8 Jan 1998

Need Help?

IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.