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The article "A 4-GHz Continuous-Time Δ-ΣADC with 70-dB DR and -74 dBFS THD in 125-MHz BW" by Muhammed Bolatkale, Lucien J. Breems, Robert Rutten, and Kofi A.A. Makinwa, published in IEEE Journal of Solid-State Circuits (JSSC), vol. 46, no. 12, pp. 2857-2868, Dec. 2011, was declared best of all in JSSC 2011. The authors' novel approach modifies loop filter architecture to deal with the parasitics and excess delay of the large comparator array in the 4-GHz multibit quantizer. Their five-times improvement in bandwidth compared to state-of-theart CMOS delta-sigma modulators enlarges the application domain of these ADCs, enabling them to compete with high speed architectures like pipeline ADCs. A detailed review of the article is provided.