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Vectorless power grid verification is a powerful method that evaluates worst-case voltage noises without detailed current waveforms using optimization techniques. It is extremely challenging when considering RLC power grids because inductors are difficult to tackle and multiple time steps should be evaluated after the discretization of the system equation. In this paper, we study integrated RLC power grids with both VDD and GND networks, and introduce transient constraints to restrict the waveform of each current source for sign-off verification. We rigorously prove that the vectorless verification can be decomposed into two subproblems-the well-studied power grid transient analysis problem and a linear programming (LP) problem that optimizes an affine function of currents under current constraints-and propose to verify the power grid by transient simulation and noise optimization. A variable reduction algorithm is further proposed to generate reduced-size LP problems with a user-specified error tolerance, so that the conservative bounds of voltage noises can be computed efficiently. Experimental results show that the proposed algorithm achieves significant speedup (e.g., up to more than 100× with 5 mV error) over the standard LP solver in solving the LP problems, and the proposed transient constraints make the noise estimations more realistic.