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A 75-µW, 16-Channel Neural Spike-Sorting Processor With Unsupervised Clustering

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3 Author(s)
Karkare, V. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, Los Angeles, CA, USA ; Gibson, S. ; Markovic, D.

Energy-efficient spike-sorting DSPs are necessary to allow for the real-time processing of multi-channel, wireless, implantable neural recordings. Online, unsupervised clustering forms an integral part of on-chip spike sorting. However, previous spike-sorting DSPs did not include unsupervised clustering due to the large memory required for its implementation. We demonstrate the first multi-channel spike-sorting DSP chip that includes online, unsupervised clustering. On-chip clustering has been made possible by using a two-stage implementation of an online clustering algorithm, a noise-tolerant distance metric, and selectively clocked high-VT register banks. The 16-channel spike-sorting chip, implemented in a 65-nm CMOS process, has a power dissipation of 75 μW at a supply voltage of 270 mV. The implementation of on-chip clustering provides a 240× reduction in the output data rate, which is 3× higher than the data-rate reduction obtained from previous spike-sorting DSP chips.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 9 )