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Scalability, power efficiency, and shorter time to market due to design reuse have favored the adoption of homogeneous multicore chips with identical processing units (cores) integrated together, offering enhanced computational power. Furthermore, chips with identical cores help cope with increasing defect rates in delivering reasonable yield levels via the utilization of spare cores. In this paper, we propose a comparison-based test access mechanism (TAM) that is capable of handling spare identical cores. The proposed TAM guarantees the test of a chip through minimum bandwidth in minimum test time, while ensuring zero yield loss in the presence of spare identical cores, as its design is driven by the number of spare cores on the chip. The proposed solution also enables the identification of all the good cores in usable chips, supporting models where chips are priced based on the number of good cores. Furthermore, we provide a tradeoff analysis that enables the designers to make an informed decision regarding yield loss versus area cost. We also extend the proposed TAM by adding efficient diagnostic features, and adapting it for low-power test.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:32 , Issue: 7 )
Date of Publication: July 2013