By Topic

Device Delay in GaN Transistors Under High Drain Bias Conditions

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

9 Author(s)
Dong Seup Lee ; Microsystems Technology Laboratories, Massachusetts Institute of Technology, Cambridge, MA, USA ; Oleg Laboutin ; Yu Cao ; Jerry Wayne Johnson
more authors

This letter studies the drain delay caused by the extension of the effective gate length in high-frequency GaN high electron mobility transistors. It is shown that the drain delay is mainly reflected in the gate-to-source capacitance (Cgs) of the device. The ratio of Cgs and transconductance (gm) is then used to accurately extract the drain delay and the result is compared with other extraction methods reported in the literature. Finally, we will use this new extraction technique to explain why short channel GaN devices show higher drain delay than longer channel transistors.

Published in:

IEEE Electron Device Letters  (Volume:34 ,  Issue: 7 )