By Topic

Implementing degradable processing arrays

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Goldberg, S.R. ; Buffalo State Coll., NY, USA ; Upadhyaya, S.J.

Today's burgeoning multimedia and network technology require large high-performance processing arrays. Conventional chip packaging and board-level integration cannot meet operating speeds in these high-performance systems. In addition, large systems require technologies that provide reliable, single packaging. The main focus of this work is to demonstrate the feasibility of building reliable systems using MCMs, with special attention to implementation issues. A simple approach employing the gracefully degradable paradigm facilitates the continued operation of a faulty array that the system would otherwise discard. The scheme identifies and makes provision to extract healthy subarrays that retain original topology, and requires a small number of transistor switches. By exploiting various implementation options of MCMs, the technique poses no increase to primary circuit area. We must identify the topology of the system to incorporate the gracefully degrading scheme. An application will dictate the utility derived from various levels of degradation. The scheme has provision for extracting one or two subsystems for continued operation. By following the steps outlined for the tree architecture, it is possible to extend the algorithm to other topologies. The general hardware layout must include switches to provide connectivity between system I/O and all subsystems that can potentially take on the role of a boundary node

Published in:

Micro, IEEE  (Volume:18 ,  Issue: 1 )