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Implementing degradable processing arrays

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2 Author(s)
S. R. Goldberg ; Buffalo State Coll., NY, USA ; S. J. Upadhyaya

Today's burgeoning multimedia and network technology require large high-performance processing arrays. Conventional chip packaging and board-level integration cannot meet operating speeds in these high-performance systems. In addition, large systems require technologies that provide reliable, single packaging. The main focus of this work is to demonstrate the feasibility of building reliable systems using MCMs, with special attention to implementation issues. A simple approach employing the gracefully degradable paradigm facilitates the continued operation of a faulty array that the system would otherwise discard. The scheme identifies and makes provision to extract healthy subarrays that retain original topology, and requires a small number of transistor switches. By exploiting various implementation options of MCMs, the technique poses no increase to primary circuit area. We must identify the topology of the system to incorporate the gracefully degrading scheme. An application will dictate the utility derived from various levels of degradation. The scheme has provision for extracting one or two subsystems for continued operation. By following the steps outlined for the tree architecture, it is possible to extend the algorithm to other topologies. The general hardware layout must include switches to provide connectivity between system I/O and all subsystems that can potentially take on the role of a boundary node

Published in:

IEEE Micro  (Volume:18 ,  Issue: 1 )