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A tracking clock recovery receiver for 4-Gbps signaling

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3 Author(s)
Poulton, J. ; North Carolina Univ., Chapel Hill, NC, USA ; Dally, W.J. ; Tell, S.

We previously described a design for a 4-Gbps signaling system that uses transmitter equalization to overcome the frequency-dependent attenuation in transmission lines due mainly to skin effect and dielectric absorption. Since then, at least one other group has built an experimental system that uses a similar approach. We present here experimental results from an implementation of this idea in 0.5-micron CMOS, showing the effectiveness of a simple transition-filter equalization technique. Our experimental chip uses a tracking clock recovery receiver, in which a 21-phase clock is servoed to center every other clock on the center of the data “eye”. Although oversampling clock recovery can reject jitter up to the lesser of the minimum transition frequency or the data clock frequency, it introduces quantization jitter of ∓/2k of the bit cell, where k is the number of samples per cell. Tracking recovery gives better performance when there is little jitter above the cut-off frequency of the tracking control loop, avoids quantization jitter entirely, and allows transmitter encoding with much longer run lengths. Electrical measurements in very high speed signaling systems are quite difficult to perform with conventional instrumentation, particularly for on-chip signals. To solve this problem, our design contains simple CMOS analog samplers that enable observation of on-chip signals

Published in:

Micro, IEEE  (Volume:18 ,  Issue: 1 )

Date of Publication:

Jan/Feb 1998

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